The impact of transient failures on microprocessor systems cache reliability

The impacts of transient failures on cache reliability regarding the data, address tags, and status bits are considered. The behavioral model of data elements, address tags, and status bits reflecting their vulnerability to transient failures is proposed. For some applications, to increase fault tolerance, it is recommended to use a cache with write-through instead of a cache with write-back. It is shown that in multiprocessing systems the sensitivity of status bits to transient failures can be lowered by using the write protocol with updating instead of write protocol with invalidation.